In the manufacture of integrated circuit devices, system level integration on a single substrate is desirable for achieving higher system functionality and performance. Multichip modules (MCMs) permit a plurality of integrated circuit chips with unique functions and from different processing technologies to be integrated into a system. In an MCM, a group of highly functional devices is interconnected on a substrate; the substrate may have a multilayer structure to provide interconnection wiring for the chips. For example, U.S. Pat. No. 4,489,364, assigned to International Business Machines Corporation, discloses a ceramic chip carrier for supporting an array of chips by means of solder balls, such as controlled-collapse chip connections (C4s). Such MCMs tend to be expensive, due to their multilayered ceramic structure, and require significantly more area than the combined area of the chips.
Another trend in device manufacturing is the inclusion of several different functions on a single chip (a "system on a chip"), which generally requires both an increased chip size and a more complicated manufacturing process. These factors both tend to depress manufacturing yield. One method of maintaining acceptable yields is to manufacture smaller chips with specific functions ("macro chips"), and then to integrate those chips on a single silicon substrate. To maintain the advantages of the system-on-a-chip approach, it is necessary to mount these macro chips on the silicon substrate in close proximity and with precise alignment, and with minimal added complexity in the overall process.
Recently, a manufacturing process has been proposed for forming a dense arrangement of chips on a silicon substrate or carrier wafer, using a silicon guide wafer. This process is described in detail in U.S. application Ser. No. 09/165,280, the disclosure of which is incorporated herein by reference. Briefly, the process involves bonding chips 4, 5 to a guide wafer 1, as shown in FIG. 1A. The chips are aligned to the guide wafer using depressions 6 etched in the chips (in kerf areas between active areas 201) which match mesas 2 formed in the guide wafer 1. The backside surfaces 31, 32 of the chips are then planarized to a level 33 and attached to a permanent substrate 34 (see FIG. 1B). The guide wafer 1 is removed, after which the exposed cavities 6 in the chips are filled (see FIG. 1C).
The bonding and removal of the chips to and from the guide wafer have presented manufacturing difficulties. Specifically, the chips were mated to the guide wafer using (111) crystallographic mesas and depressions and required appropriate photopattern alignment with the crystal orientations. Furthermore, the mating relied on oxide-oxide bonding (a sensitive surface activation process dependent on van der Waals forces). Accordingly, the bonding was highly sensitive to the cleanliness of the surfaces. In addition, this process required the use of the kerf area for the formation of the depression, thereby increasing the size of the chip. Also, the previous method of removing the guide wafer required physical grinding, polishing or wet etching of the wafer.
In view of these difficulties with the previously disclosed process, there remains a need for a fabrication process in which a dense arrangement of chips can be bonded to a carrier substrate with high manufacturing yield.